TL;DR: Huawei says its Tau Scaling Law and LogicFolding architecture can lift density and performance by shortening signal paths across devices, circuits, chips, and systems, with 381 chips reportedly mass-produced under the framework and first LogicFolding Kirin products planned for fall 2026.[1][3] Intel, meanwhile, says 18A-P is in risk production with 9% higher performance at iso-power or 18% lower power at iso-performance versus 18A, while showing longer-range work in CFETs, GaN-on-silicon, and ruthenium interconnects.[2] The real story isn't China versus America. It is transistor scaling versus system scaling.
Huawei isn't just pitching a new chip architecture, it's trying to rewrite the scoreboard for semiconductor progress.
Intel is not just updating a node, it is trying to prove the old scoreboard still works if you add backside power, new transistor options, better thermals, and credible foundry execution.
That is why these two announcements belong in the same article. Huawei's May 25 Tau Scaling Law presentation and Intel Foundry's June 16 VLSI update look like separate stories. One is a sanctions-era Chinese design thesis. The other is an American foundry credibility campaign. But underneath, both say the same uncomfortable thing: the future of chips will not be explained by node names alone.
What's often overlooked is that Huawei and Intel are not arguing about whether scaling continues. They are arguing about what should count as scaling. Huawei wants to move the conversation from lithographic shrink to signal delay, layout, stacking, and full-system co-optimization. Intel wants to show that advanced nodes still matter, but only when bundled with power delivery, interconnect, materials, and thermals.
The old chip race was easy to narrate: smaller transistors, denser chips, faster products. The new one is messier. It is density plus data movement. Power plus routing. Heat plus packaging. Silicon plus software demand. That is not a cleaner story, but it is probably the real one.
Why This Matters Now
Huawei's claim reframes chip progress around τ, signal delay, vertical design, and architectural efficiency instead of pure lithographic shrink. Intel's 18A-P update gives the market a measurable near-term benchmark: 9% more performance at the same power or 18% lower power at the same performance versus 18A. Put together, the message is simple: future chips will be judged by performance per watt, thermal density, interconnect quality, memory proximity, package design, and manufacturability, not node branding alone.
Huawei's Bet: If You Can't Shrink Fast Enough, Fold The Logic
Huawei's Tau Scaling Law is best understood as a strategy born from constraint. The company does not have free access to the same EUV lithography toolchain that TSMC, Samsung, and Intel can plan around. So Huawei is trying to make the absence of that toolchain less decisive.
In its official announcement, Huawei says Tau Scaling replaces geometric scaling with time scaling as a guiding principle for future semiconductors and electronic systems.[1] The idea is not mystical. τ represents time constants and delay. If progress from smaller transistors gets harder, then reduce the time it takes signals and data to move through the system.
That leads to LogicFolding. Huawei describes it as an architecture that breaks down the physical boundaries of traditional circuit layouts, shortens critical-path wiring, reduces resistive and capacitive load, and improves transistor density and circuit performance.[1] CNBC reported that Huawei plans to use the approach in Kirin smartphone chips this fall, while claiming a path to 1.4 nanometer-class capabilities by 2031.[3]
Let's be clear: that is not the same as saying Huawei has built a true 1.4 nanometer manufacturing process. It has not shown that. The careful reading is that Huawei is describing an effective density and performance path based on architecture, folding, stacking, and co-design. That is still important, but it is different from EUV-driven node leadership.
How Huawei Wants Tau Scaling To Work
Shorten data movement
Treat propagation delay as the bottleneck, not only transistor size.
Reorganize circuit layouts
Use LogicFolding to reduce critical-path wiring and signal load.
Stack and fold compute paths
Move from flat layout thinking toward denser vertical structures.
Co-design chips and systems
Coordinate devices, circuits, chips, software, and workloads around the same latency target.
Ship proof in products
Move from a framework to Kirin chips, AI accelerators, and eventually data-center systems.
Here's the genius: Huawei is not trying to beat ASML at ASML's game. It is trying to make ASML's game less decisive.
That does not make the technical risk disappear. It changes where the risk lives. The bottlenecks move into thermal density, packaging complexity, EDA tooling, yield, debug, and design portability. A folded architecture can compress distance, but it can also concentrate heat. It can improve effective density, but it can also make manufacturing and validation harder. Architecture can compensate for lithography, but it cannot repeal manufacturing physics.
Intel's Counter: 18A-P Is A Manufacturing Credibility Test
Intel's VLSI 2026 announcement has less drama and more numbers. That is the point.
Intel Foundry says 18A-P, the first performance enhancement in the 18A family, has entered risk production.[2] Risk production is not volume production. It is the stage where the manufacturing flow is being qualified ahead of higher-volume commercial use. For Intel, that distinction matters because the foundry story depends on credibility, repeatability, and customer trust.
The 18A-P claims are concrete: 9% higher performance at the same power or 18% lower power at the same performance compared with Intel 18A.[2] Intel also disclosed 20-40% improved thermal resistance, 10-30% improved via resistance, Power Boost as a dual-contact low-resistance transistor option, PMOS strain engineering, and design-rule compatibility with 18A.[2]
Intel 18A-P: The Near-Term Proof Points
Intel's VLSI pitch is not one miracle. It is a stack of smaller improvements that must add up to a credible foundry platform.
Intel says 18A-P delivers 9% higher performance at iso-power versus 18A.
Intel says 18A-P can deliver 18% lower power at iso-performance versus 18A.
Intel cites improved thermal resistance through materials and design changes.
Intel says geometry and materials optimizations improved vertical interconnect resistance.
Intel reports 10x dynamic voltage droop reduction in its backside-power and gate-all-around work.
18A-P is being qualified, not yet proven as broad volume production for external customers.
While competitors chase the language of breakthrough, Intel is trying to sell the discipline of repeatability. That is less fun on social media. It is exactly what foundry customers care about.
The uncomfortable truth is that Intel can be technically right and still commercially exposed. A risk-production node with good claims does not automatically win hyperscale customers. Intel has to prove yields, design ecosystem maturity, pricing, capacity, and delivery discipline. A foundry roadmap is not a press release. It is a customer trust machine.
The Materials War Behind The Marketing
The most important part of Intel's announcement was not 18A-P alone. It was the future-looking stack around it.
Intel showed monolithic CFET inverters with vertically stacked NMOS and PMOS devices at a 45nm gate pitch, a path beyond today's gate-all-around transistor era.[2] It discussed 300mm monolithic GaN plus silicon integration for power management, including silicon logic with gallium nitride power devices.[2] It also disclosed subtractive ruthenium interconnect with airgap integration, pointing toward lower capacitance and improved resistance-capacitance scaling as copper wiring becomes harder to push.[2]
These are not all shipping in commercial 18A-P products. They are roadmap pieces. But roadmap pieces matter because the next semiconductor race is increasingly a materials and integration race.
The New Scaling Stack
CFET
Stacks complementary transistors vertically, pushing density beyond gate-all-around devices.
Backside power
Moves power delivery behind the transistor layer, freeing frontside routing and reducing droop.
Ruthenium
Targets interconnect resistance and capacitance as wires become the limiting system.
GaN on silicon
Integrates power devices and control logic for more efficient power management.
Advanced packaging
Turns multiple chiplets, memory, and accelerators into one performance system.
Thermal design
Determines whether high-density silicon can sustain performance under real workloads.
The uncomfortable truth: the transistor is no longer the whole product. The wiring, heat, power, package, and software demand now decide whether the transistor can matter.
This is why the Huawei and Intel stories rhyme. Huawei is attacking wire delay through a new law and folded design language. Intel is attacking power delivery, interconnect, thermal resistance, device options, and vertical transistor structures. One is framed as strategic escape. The other is framed as foundry execution. Both are systems arguments.
The Strategic Split: Huawei Needs Sovereignty, Intel Needs Customers
Huawei's pressure is sovereignty. Intel's pressure is customers.
Huawei needs a way to keep Chinese compute moving despite tool restrictions. It benefits from a framework that says progress is not only about who owns the smallest lithographic node. It needs domestic AI infrastructure credibility. It needs smartphone leadership against Apple. It needs a way to tell customers, regulators, and engineers that the road does not end at the EUV gate.
Intel needs something different. It needs external customers to believe Intel Foundry is no longer a promise machine. It needs 18A and 18A-P to be viewed as platforms, not lab slides. It needs to turn PowerVia, RibbonFET, and process co-optimization into a repeatable commercial offering. It also needs to show that U.S. semiconductor industrial policy can produce a real alternative to TSMC concentration.
Two Scaling Philosophies
| Feature | Huawei Tau / LogicFolding | Intel 18A-P And Beyond |
|---|---|---|
| Strategic pressure | Reduce dependence on restricted leading-edge lithography and foreign supply chains. | Rebuild foundry credibility and win external customer trust. |
| Scaling method | Shorten signal paths through folding, layout changes, stacking, and system co-design. | Improve process performance through transistor, power, interconnect, thermal, and design-rule execution. |
| Main proof point | Huawei claims 381 mass-produced chips under Tau and LogicFolding products planned for Kirin. | Intel says 18A-P is in risk production with measured performance and power deltas. |
| Main bottleneck | Thermals, yield, EDA tooling, packaging complexity, and independent validation. | Yield, customer adoption, cost, capacity, and consistency of delivery. |
| Best-case outcome | China narrows the effective performance gap without matching every Western toolchain step. | Intel becomes a credible second source for advanced AI and data-center silicon. |
The real story isn't who has the better slogan. It is who can make their scaling philosophy survive yield, cost, thermal limits, and customer scrutiny.
What This Means For Future Chips
Node names will still matter. Anyone saying otherwise is trying too hard. A company with a better manufacturing process has a real advantage.
But node names will matter less by themselves. The future comparison will be performance per watt, package bandwidth, memory locality, rack-level thermals, chiplet density, power delivery, software utilization, supply-chain resilience, and total system cost. AI accelerators, in particular, punish wasted data movement. If a model workload spends too much energy moving bits instead of computing on them, the node number stops saving you.
Who Gets Hit By The Post-Moore Shift
AI labs
Better economics if chipmakers reduce data movement and memory bottlenecks instead of only adding transistor count.
Smartphone vendors
More room for performance under strict thermal envelopes, especially if folded layouts improve useful density.
Foundries
More pressure to sell complete technology platforms, not just named process nodes.
Governments
Semiconductor sovereignty becomes an architecture, packaging, software, and materials problem, not only a fab problem.
Investors
Roadmap claims need manufacturability filters. A beautiful law does not equal shipped margin.
Let's be clear: the next chip cycle will not be won by the company with the most elegant law. It will be won by the company that turns that law into shipped silicon at acceptable yield.
The Node Name Trap
The biggest mistake is treating Huawei's 1.4 nanometer-class language and Intel's 18A-P claims as directly comparable. Huawei is describing an effective scaling framework shaped by architecture and integration. Intel is describing a process platform with measured performance and power deltas. The strategic comparison is real, but the metrics are not interchangeable.
The Takeaway: Moore's Law Didn't End, It Lost Its Monopoly
The real story isn't the death of Moore's Law. It is the rise of competing scaling regimes.
Huawei's Tau Scaling Law is a strategic reframing born from constraint. It says that if the transistor shrink race is blocked or economically exhausted, progress can still come from reducing delay across the full compute system. Intel's 18A-P roadmap is a credibility campaign built around measurable execution. It says advanced manufacturing can keep improving, but only when transistors, power, interconnects, materials, thermals, and design rules move together.
The future of chips will not be decided by who names the smallest node. It will be decided by who controls the full stack of density, power, heat, interconnect, packaging, and software demand.
That is the future of semiconductors. Not one race, but several layered on top of each other. Foundries will still fight over nodes. Nations will fight over toolchains. AI companies will fight over watts. Device makers will fight over thermals. Chip designers will fight over data movement.
The old scoreboard was small enough to fit in a node name. The new scoreboard is the whole system.
Key Takeaways
Huawei's Tau Scaling Law should be read as an effective scaling framework, not proof of true 1.4 nanometer manufacturing parity.
Intel 18A-P matters because it is a near-term manufacturing credibility test, not because it ends Intel's foundry doubts by itself.
CFETs, backside power, GaN integration, ruthenium interconnects, and advanced packaging all point to the same post-Moore direction.
Future chip leadership will be measured by system performance per watt, not just transistor density.
The companies that win will be the ones that convert theory into yield, cost control, and customer trust.
Sources & References
Key sources and references used in this article
| # | Source | Outlet | Date | Key Takeaway |
|---|---|---|---|---|
| 1 | Huawei presents Tau Scaling Law at IEEE ISCAS 2026 | Huawei | May 25, 2026 | Huawei frames Tau Scaling as a shift from geometric scaling to time scaling, with LogicFolding used to shorten signal delay and improve density and performance. |
| 2 | Intel Foundry details 18A-P and future innovations at VLSI 2026 | Intel Newsroom | June 16, 2026 | Intel says 18A-P entered risk production with 9% higher performance at iso-power, 18% lower power at iso-performance, and roadmap work in CFET, GaN, and ruthenium. |
| 3 | Huawei plans new smartphone chips this fall | CNBC | May 25, 2026 | Reports Huawei's plan to use LogicFolding in Kirin smartphone chips and discusses skepticism around 1.4 nanometer-equivalent claims. |
| 4 | China's Huawei touts chip design breakthrough | NBC News | May 25, 2026 | Summarizes Huawei's claim that LogicFolding can reduce dependence on conventional transistor shrinking and highlights cost, power, heat, and integration risks. |
| 5 | Is Huawei's new chip scaling law a true breakthrough, or mere hype? | South China Morning Post | May 30, 2026 | Explains the geopolitical context and the skepticism around whether Tau Scaling is a true breakthrough or a strategic reframing. |
| 6 | IBM unveils sub-1 nanometer nanostack chip technology | IBM | June 25, 2026 | Shows that vertical transistor structures and nanostack architectures are part of a broader industry movement beyond planar scaling. |
| 7 | IBM chip technology could extend Moore's Law another decade | MIT Technology Review | June 25, 2026 | Provides independent context for vertical transistor stacking, CFETs, and why future density gains increasingly come from building upward. |
| 8 | Huawei's chip queen unveils Tau Scaling Law | The Next Web | June 15, 2026 | Secondary analysis of Huawei's LogicFolding architecture, Ascend roadmap context, and likely thermal and yield constraints. |
| 9 | Why Huawei's new chipmaking plan has investors buzzing | The Business Times | May 27, 2026 | Frames Huawei's Tau Scaling as an investor and industry signal that China is looking beyond lithographic shrink as the sole path to competitiveness. |
| 10 | Intel Foundry details process milestones and future innovation | Intel Corporation | June 16, 2026 | Provides Intel's investor-relations version of the 18A-P, backside power, CFET, GaN, and ruthenium VLSI announcements. |
Last updated: June 27, 2026
